1. Field of the Invention
This invention relates to a semiconductor device and a manufacturing method of a semiconductor device.
2. Description of the Related Art
In recent years, miniaturization of semiconductor devices such as DRAM (Dynamic Random Access Memory) has been pursued. When the transistor gate length of a transistor is reduced, the short channel effect in the transistor becomes pronounced, and problems arise of increased subthreshold current and reduced threshold voltage (Vt) of the transistor.
Further, if the impurity concentration in a semiconductor substrate is increased in order to suppress drop of the transistor threshold voltage (Vt), joint leak current will be increased.
Therefore, when DRAM (Dynamic Random Access Memory) is used as a semiconductor device and a DRAM memory cell is miniaturized, degradation of refresh characteristics poses a serious problem.
In order to avoid such problems, Japanese Laid-Open Patent Publication No. 2006-339476 (Patent Document 1) and No. 2007-081095 (Patent Document 2) disclose a so-called trench-gate transistor (also called “recess channel transistor”) in which a gate electrode is embedded in a trench formed in a principal surface of a semiconductor substrate.
The use of a trench-gate transistor makes it possible to ensure a physically sufficient effective channel length (gate length), and to realize a DRAM having minute cells with a minimum processing size of 60 nm or less.
Patent Document 2 discloses a DRAM having two trenches formed in a semiconductor substrate to be adjacent to each other, a gate electrode formed in each of the trenches via a gate insulating film, a first impurity diffusion region formed on a principal surface of the semiconductor substrate between the two gate electrodes and serving as a common impurity diffusion region for the two gate electrodes, and a second impurity diffusion region formed on the principal surface of the semiconductor substrate located on an element isolation region side of each of the two gate electrodes.